1. Field of the Invention
The present invention relates to a semiconductor chip, a semiconductor device on which a semiconductor chip is mounted, and a process for producing a semiconductor device, and more specifically to a semiconductor chip, such as a DRAM, an SRAM, a flash memory, a central processing unit (CPU), a micro-processing unit (MPU) or a digital system processor (DSP), having a terminal for making a test thereof easy, a semiconductor device on which such a semiconductor chip is mounted, and a process for producing such a semiconductor device.
2. Description of the Background Art
In many cases, a system composed of a combination of a memory such as a DRAM, an SRAM or a flash memory with a CPU, an MPU or a DSP is produced and used as one system unit. FIG. 10 is a view illustrating an example produced at the earliest times when such a system semiconductor device was distributed. A memory semiconductor chip 110 is connected to a CPU 111 and a DSP 112, which are logic semiconductor chips, through its leads 125 and substrate wiring 119, and they are mounted on a single wiring substrate 107. Distribution of such a system semiconductor device made it possible to select and use a desired system without requiring many steps for design of the system and so on. A drawback of this system semiconductor device is that its size becomes large so that it is unsuitable for use in a portable terminal or the like device.
FIG. 11 is a view illustrating a one-chip consolidation semiconductor device wherein plural semiconductor circuits are consolidated on a plane to make its size small. This device is a device suggested to overcome the above-mentioned problem. In this semiconductor device, respective semiconductor blocks are integrated with each other and formed on a single semiconductor substrate. Specifically, in this one-chip consolidation semiconductor device, a memory semiconductor block 110 and a logic semiconductor block 111 are simultaneously made on a semiconductor substrate 101 in the same processing step. For this reason, semiconductor circuits having different purposes are formed on respective areas in the single semiconductor substrate. The respective semiconductor circuit blocks are connected to each other through metal wires 119 made at the same time when the semiconductor circuit blocks themselves were made. In this one-chip consolidation semiconductor device, test terminals (testing terminal) 103 that are to be connected to a tester and circuit-constituting terminals 105 that are to be connected to terminals of any other element are separately connected to wires for terminals that are extended from the respective semiconductor chips themselves, and constitute rows. It has been promoted that system semiconductor devices are made small and thin, using such a one-chip consolidation semiconductor device.
However, the above-mentioned one-chip consolidation semiconductor device has the following problem. A memory semiconductor circuit such as a DRAM has a much complicated structure and it must be produced through a very troublesome process for forming memory cells. On the other hand, a logic circuit such as a CPU has a simple structure so that the process for producing the same is also relatively simple. In the case that logic circuits are produced on a semiconductor substrate in a one-chip consolidation semiconductor device at the same time when memories are produced, blocks of the logic circuits are subjected to useless heat treatment and so on for a long time so that the performance of the system may become bad. This causes a problem that by adopting one-chip consolidation, the date of delivery of the semiconductor devices is delayed and the entire structure of the memories and the logic circuits becomes complicated so that the yield of the devices drops. Therefore, difficulty becomes larger about one-chip consolidation semiconductor devices as the devices are becoming more minute so that the capacity of their memories becomes larger.
To overcome this problem, stack-type consolidation chips as shown in FIGS. 12A and 12B are suggested (Japanese Patent Laying-Open No. 2000-114452 (2000), Japanese Patent Laying-Open No. 11-214448 (1999) and so on). FIG. 12A is a sectional view of a semiconductor device wherein semiconductor chips are stacked and mounted, and FIG. 12B is a plan view of each semiconductor chip in the semiconductor device. In FIG. 12A, respective stacked chips 110a and 110b are beforehand produced and their performance is tested before the chips are stacked. Thus, it is checked whether the chips get through the test or not. In a packaging step, the following is merely performed: terminals 105a and 105b of the semiconductor chips mounted on a die pad 106 are connected through a wire 109 and the terminal 105b and a lead terminal 106a are connected through another wire 109. Therefore, the logic semiconductor chip is not subjected to any long-sustained heat treatment required for producing memories, so that a high yield can be kept in the production of large-scale integrated system semiconductor devices. As illustrated in FIG. 12B, all of the terminals of the semiconductor chips constituting a package are composed of circuit-constituting terminals 105. The semiconductor chips are tested using the circuit-constituting terminals.
However, in the semiconductor chips having only the circuit-constituting terminals shown in FIG. 12B, the circuit-constituting terminals also function as test terminals. Thus, it may be impossible that appropriate wiring for terminals is led out from a site necessary for the test and then the test is performed. Specifically, no terminals may be set up at sites where an examiner wants to obtain testing signals actually since the real terminals are set up mainly to constitute circuits. For a thoroughgoing test, it is necessary that respective terminals of the individual terminal output an intense signal to a test device. For this, it is necessary that a driver etc. for outputting such an intense signal are fitted up to each of the semiconductor chips. If such a driver is fitted up, problems as follows arise: parasitic capacitance is generated; the structure of the circuits becomes still more complicated; and electric current consumption increases. In circuit-design and actual production of consolidated semiconductor chips, it is a heavy load to add such drivers and the like elements. It is therefore desired to avoid the fitting-up of the driver in each of the chip circuits. However, if a driver as described above is not fitted up to a certain semiconductor chip, the output signal is weak. As a result, for example, the semiconductor chip cannot be tested at a high speed. Needless to say, it is desired that the performance of semiconductor chips having a minute and complicated circuit is checked in a thoroughgoing test and then the chips are forwarded.
An object of the present invention is to provide a semiconductor chip that can easily be subjected to a thoroughgoing test without imposing a burden on its circuit; a semiconductor device on which such a semiconductor chip is mounted; and a process for producing such a semiconductor device.
The semiconductor chip of the present invention includes a first test terminal connected to a terminal line that extends from a body of the chip, the first test terminal being a terminal for being jointed to a test device; and a circuit-constituting terminal branched from the terminal line and connected to the terminal line, the circuit-constituting terminal being a terminal for being connected to any other circuit element.
Since the circuit-constituting terminal and the first test terminal are terminals different from each other, this structure makes it possible to arrange the two terminals at a position convenient for the structure of the circuit and at a position convenient for a test, respectively. The above-mentioned other circuit element may be a semiconductor chip or a circuit element that is not any semiconductor chip. As it is naturally assumed, the present semiconductor chip may include not only the above-mentioned terminals but also a power source terminal for the body of the semiconductor chip, a ground terminal and the like terminals well-known in the present field. The present chip also includes not only the first test terminal and the circuit-constituting terminal that are branched from each other but also a line for a terminal to which only the test terminal is connected and a line for a terminal to which only the circuit-constituting terminal is connected. The semiconductor chip of the present invention corresponds to a memory semiconductor chip such as a DRAM, an SRAM, a flash memory or an EPROM (erasable programmable read only memory); or a logic semiconductor chip such as a CPU, an MPU or a DSP.
The semiconductor chip of the present invention may further include, for example, a second test terminal connected to a test terminal line.
The test terminal line wherein only the second test terminal is connected in the above description means a line, for a terminal, to which no circuit-constituting terminal is connected. According to this structure, the test terminal can be set up by extending the terminal line from a body position convenient for a test, regardless of any circuit-constituting terminal, so that the test can be performed. Therefore, the property of the semiconductor chip such as a complicated memory can be thoroughly tested.
The semiconductor chip of the present invention, may further include, for example, a driver disposed at a position between the first test terminal and the branch point.
In the semiconductor chip of the present invention, for example, the driver is for amplifying a signal to the test device.
This structure makes it possible to test the semiconductor chip sufficiently at a high-speed without setting up, to the body of the semiconductor chip, a circuit for outputting a signal having an intensity unnecessary for the circuit structure made together with any other block, for example, a driver. Therefore, the semiconductor chip whose performance has been checked can be provided without generating parasitic capacitance in the body or imposing excessive burden on the circuit structure. The driver means a circuit element for amplifying a signal intensity in order that a weakly-driven signal can cope with a heavy load. Specifically, the driver corresponds to an inverter circuit and a lot of other amplifying circuit elements. The test terminal can be referred to, in the case that an outputting terminal and an inputting terminal are divided from each other, as an outputting terminal.
In the semiconductor chip of the present invention, for example, the driver is for transmitting a signal from the test device to the semiconductor chip.
Since the intensity of an input signal from the test device can be freely adjusted by the test device, the above-mentioned driver is a driver having a property for shaping waveforms rather than a driver having a property for increasing driving power. Therefore, its channel width may be relatively small. Needless to say, however, the above-mentioned drive may be a driver for increasing driving power. The test terminal may be referred to, in the case that an inputting terminal and an outputting terminal are divided from each other, as the inputting terminal.
In the semiconductor chip of the present invention, for example, the driver is composed of an inverter circuit including a Metal Oxide Semiconductor (MOS) transistor.
This structure makes it possible to form the inverter circuit including the MOS transistor compactly between the branch portion where the circuit-constituting terminal is branched and the test terminal. For this reason, a sufficiently intense output signal for a test can be outputted without imposing a burden on the body of the semiconductor chip.
In the semiconductor chip of the present invention, for example, the following is desired: the inverter circuit is composed of multistage inverter circuits; and in two MOS transistors in the inverter circuits adjacent to each other, the channel width of the MOS transistor in the inverter circuit nearer to the side to which the signal is transmitted is longer.
This simple structure makes it possible to output a sufficiently intense testing signal without imposing a heavy burden. In order to obtain a signal whose rise is sharp to generate no delay, the extent for increasing the channel width is as follows. The fanning-out ratio, which is the ratio between the channel width of any inverter circuit and that of the inverter circuit next thereto, is desirably from 2 to 5.
The semiconductor chip of the present invention may further include, for example, a driver power source terminal for the driver.
By separating a power source terminal of the semiconductor chip body from the driver power source terminal for the test terminals, it is possible to output more surely a signal having an intensity sufficient for a test and input more surely a signal whose waveform is shaped without increasing the parasitic capacitance of the circuit of the chip body or making the circuit structure complicated. Wires for the driver power source are extended from the driver power source terminal and connected to the respective drivers.
In the semiconductor chip of the present invention, for example, a plurality of the circuit-constituting terminals and a plurality of the first test terminals may be arranged in the form of rows along an edge of the semiconductor chip, as viewed in plan.
By arranging the circuit-constituting terminals along the edge, the entire circuit can be made in the state that the length of the lines between the elements is short. By arranging the first test terminals along the edge, the length of the lines from the branch portions of the circuit-constituting terminals can also be made short.
In the semiconductor chip of the present invention, for example, the following desired: the first test terminals are arranged along the edge and at positions nearer to the edge than the circuit-constituting terminals are arranged, as viewed in plan.
By making the first test terminals nearer to the edge than the circuit-constituting terminals, the first test terminals can be separated off after completion of the test and before packaging, for example, at the time of dicing. Thus, the semiconductor chip can be made small-sized.
In the semiconductor chip of the present invention, for example, the following is desired: a mark is made to divide the row of the first test terminals from the row of the circuit-constituting terminals.
This mark makes it possible to make a cutting portion clear and cut the edge portion at an appropriate position without fail. This mark may be a merely drawn line, or a cutting groove, a notch or perforations making the cutting or separation easy.
The semiconductor chip of the present invention may be, for example, a memory semiconductor chip.
By setting up the circuit-constituting terminal and the first test terminal in the memory semiconductor chip as described above, it is possible to check easily the performance of the memory whose circuit is complicated and whose quality is frequently insufficient because of a special treatment in the process for producing the memory.
The semiconductor device of the present invention includes a first semiconductor chip including a test terminal connected to a line, for terminals, extending from a body of the chip, the test terminal being a terminal for being jointed to a test device, and a circuit-constituting terminal branched from the terminal line and connected to the terminal line, the circuit-constituting terminal being a terminal for being connected to any other circuit element; a second semiconductor chip comprising a circuit element and a terminal, said terminal being connected to the circuit-constituting terminal of the first semiconductor chip; and a circuit substrate for packaging the first and second semiconductor chips.
This structure makes it possible to obtain the semiconductor device wherein the performance of the respective semiconductor chips has been checked. In this packaged semiconductor device, the respective semiconductor chips are usually stacked but the respective semiconductor chips may be two-dimensionally arranged.
In the semiconductor chip of the present invention, for example, the following is desired: the test terminal in the semiconductor chip has been removed.
This structure makes it possible to make the respective semiconductor chips small-sized so that the packaged semiconductor device can be made small-sized.
The process for producing a semiconductor device of the present invention is a process for producing a semiconductor device wherein semiconductor chips, each of which includes a circuit-constituting terminal and a test terminal which are branched from a terminal line, are mounted on/over a circuit substrate. This producing process includes a test step of performing a test by bringing a probe into contact with the test terminal when the semiconductor chips are in a wafer state; a dicing step of cutting the semiconductor chips in the wafer state from each other; and a circuit element connecting step of connecting the circuit-constituting terminal in the semiconductor chip on the circuit substrate to a terminal of any other circuit element on the circuit substrate.
By performing a probe-contacting test using the test terminal exclusive for the test in the state that the semiconductor chip is in a wafer state, the semiconductor chips having insufficient performance can be checked and removed. Therefore, it is possible to save useless labor for mounting the semiconductor chips having insufficient performance and improve efficiency of the production. The wording xe2x80x9ca member on the substratexe2x80x9d means xe2x80x9ca member directly on the substratexe2x80x9d or xe2x80x9ca member superposing on any other circuit element, the substratexe2x80x9d.
In the semiconductor device producing process of the present invention, for example, the dicing step may include a test terminal removing step of cutting and removing the test terminal from semiconductor chip.
By removing the test terminal in the dicing step, the respective semiconductor chips can easily be made small-sized. As a result, the semiconductor device can be made small-sized.
In the semiconductor device producing process of the present invention, for example, the following is desired: the circuit element connecting step includes a stacking step of stacking two or more semiconductor chips, at least one of which is the above-mentioned semiconductor chip (including the circuit-constituting terminal and the test terminal which are branched from each other).
This process makes it possible to package the respective semiconductor chips whose performance has been guaranteed at a high surface density and a high integration degree. Thus, the area of semiconductor devices having a high integration degree can be small.